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| QUAD 4-INPUT OR/NOR GATE FEATURES s s s s 500ps max. propagation delay Extended 100E VEE range of -4.2V to -5.5V True and complementary outputs Fully compatible with industry standard 10KH, 100K I/O levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E101 s Available in 28-pin PLCC package SY10E101 SY100E101 DESCRIPTION The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems. The E101 features both true and complementary outputs. BLOCK DIAGRAM D0a D0b D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d D3a D3b D3c D3d Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 PIN CONFIGURATION VCCO Q3 Q3 D3a 25 24 23 22 21 20 19 D2d D2c D2b VEE D2a D1d D1c D3b D3c D3d 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q2 Q2 VCC Q1 Q1 Q0 Q0 PLCC TOP VIEW J28-1 16 15 14 13 12 D1a D0c D0b D0a PIN NAMES Pin Dna, Dnb, Dnc, Dnd Q0-Q3 Q0-Q3 VCCO Data Inputs True Outputs Inverting Outputs VCC to Output Function VCCO Rev.: D D0d D1b Amendment: /2 1 Issue Date: May, 1998 Micrel SY10E101 SY100E101 LOGIC EQUATION Qn = Dna + Dnb + Dnc + Dnd DC ELECTRICAL CHARACTERISTICS VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND TA = -40C Symbol IIH IEE TA = 0C Min. -- -- -- TA = +25C Max. 150 36 36 TA = +85C Min. -- -- -- Parameter Input HIGH Current Power Supply Current 10EL 100EL Min. -- -- -- Typ. -- 30 30 Max. 150 36 36 Typ. -- 30 30 Min. -- -- -- Typ. -- 30 30 Max. 150 36 36 Typ. -- 30 35 Max. 150 36 42 Unit A mA AC ELECTRICAL CHARACTERISTICS VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND TA = -40C Symbol tPLH tPHL tskew tr tf Parameter Propagation Delay to Output D to Q Within-Device Skew(1) Within-Gate Skew(2) Rise/Fall Time 20% to 80% TA = 0C Min. 200 -- -- 300 TA = +25C Max. 500 -- -- 575 TA = +85C Min. 200 -- -- 300 Min. 150 -- -- 275 Typ. -- 50 25 -- Max. 550 -- -- 625 Typ. 350 50 25 380 Min. 200 -- -- 300 Typ. 350 50 25 380 Max. 500 -- -- 575 Typ. 350 50 25 380 Max. 500 -- -- 575 Unit ps ps ps ps NOTES: 1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Within-gate skew is defined as the variation in propagation delays through a single gate when driven from its different inputs. PRODUCT ORDERING CODE Ordering Code SY10E101JC SY10E101JCTR SY100E101JC SY100E101JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Ordering Code SY10E101JI SY10E101JITR SY100E101JI SY100E101JITR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Industrial Industrial Industrial Industrial 2 Micrel SY10E101 SY100E101 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 3 |
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